604 Hardware Specifications

25

Preliminary/Subject to Change without Notice

1.7 System Design Information

This section provides electrical and thermal design recommendations for successful application of the 604.

1.7.1 PLL Configuration

The SYSCLK input determines the external bus frequency at which the 604 will operate. The internal PLL

can be configured to provide an internal (processor core) frequency that is a multiple of the external bus

clock frequency. The PLL is configured by the PLL_CFG0–PLL_CFG3 signals. For a given SYSCLK (bus)

frequency, the PLL configuration signals set the internal CPU frequency of operation as shown in Table 12.

Table 12. PLL Configuration

Bus, CPU and VCO Frequencies

PLL_CFG0

to

PLL_CFG3

CPU/

SYSCLK

Ratio

Bus

16.6 MHz

Bus

20 MHz

Bus

25 MHz

Bus

33.3 MHz

Bus

40 MHz

Bus

50 MHz

Bus

60 MHz

Bus

66.6 MHz

0001

1:1

—

—

—

—

—

50

(200)

60

(240)

66.6

(266)

0100

2:1

—

—

—

—

—

100

(200)

120

(240)

133

(266)

0101

2:1

—

—

50

(200)

66.6

(266)

80

(320)

——

—

1000

3:1

—

—

—

100

(200)

120

(240)

150

(300)

——

1001

3:1

50

(200)

60

(240)

75

(300)

1100

1.5:1

—

—

—

90

(180)

100

(200)

1101

1:5:1

50

(200)

60

(240)

75

(300)

90

(360)

0011

PLL Bypass

Notes:

1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not useful, not supported,

or not tested for by the 604. VCO frequencies (shown in parenthesis in Table 12) should not fall below 180

MHz, and should not exceed 360 MHz.

2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, and the bus is set for

1:1 mode operation. The PLL-bypass mode is for test purposes only, and is not intended for functional

use.

3. PLL_CFG0–PLL_CFG1 select the CPU-to-bus ratio (1:1,1.5:1, 2:1, 3:1), PLL_CFG2–PLL_CFG3 select

the CPU-to-PLL multiplier (x2, x4).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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