MPC604ECSLASHD datasheet(9/32 Pages) NXP

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604 Hardware Specifications

Preliminary/Subject to Change without Notice

1.3.4 JTAG AC Timing Speciﬁcations

Table 8 provides the JTAG AC timing speciﬁcations.

Figure 5 provides the JTAG clock input timing diagram.

Figure 5. Clock Input Timing Diagram

Table 8. JTAG AC Timing Specifications (Independent of SYSCLK)

Num

Characteristic

Min

Max

Unit

Notes

TCK frequency of operation

MHz

TCK cycle time

62.5

—

TCK clock pulse width measured at 1.5 V

—

TCK rise and fall times

TRST setup time to TCK rising edge

—

TRST assert time

—

Boundary-scan input data setup time

—

Boundary-scan input data hold time

—

TCK to output data valid

TCK to output high impedance

TMS, TDI data setup time

—

TMS, TDI data hold time

—

TCK to TDO data valid

TCK to TDO high impedance

Notes:

1. Load capacitance = 50 pF.

2. TRST is an asynchronous signal. The setup time is for test purposes.

TCK

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

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