S29CD032J datasheet(38/76 Pages) SPANSION

38 / 76 page

S29CD-J & S29CL-J Flash Family

S29CD-J_CL-J_00_B1 September 27, 2006

Data

Sheet

(Pre limin ar y)

are selected for erasure, the entire time-out also applies after each additional sector erase command. When

the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase

commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See

Section 8.7.2, Sector Erase on page 27 for more details.

After the sector erase command is written, the system reads the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted the command sequence, then reads DQ3. If DQ3 is “1,”

the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until

the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands.

To ensure the command has been accepted, the system software check the status of DQ3 prior to and

following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last

command might not have been accepted. Table 8.9 shows the status of DQ3 relative to the other status bits.

8.8.7

RY/BY#: Ready/Busy#

The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the

Embedded Algorithms are either in progress or have been completed. If the output of RY/BY# is low, the

device is busy with either a program, erase, or reset operation. If the output is floating, the device is ready to

accept any read/write or erase operation. When the RY/BY# pin is low, the device will not accept any

additional program or erase commands with the exception of the Erase suspend command. If the device has

entered Erase Suspend mode, the RY/BY# output is floating. For programming, the RY/BY# is valid (RY/BY#

= 0) after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/

BY# is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the

RY/BY# is also valid after the rising edge of the sixth WE# pulse.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the

internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is

asserted when a program or erase operation is not executing (RY/BY# pin is floating), the reset operation is

completed in a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the

RESET# pin returns to VIH.

Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-

up resistor to VCC. An external pull-up resistor is required to take RY/BY# to a VIH level since the output is an

open drain.

Table 8.9 shows the outputs for RY/BY#, DQ7, DQ6, DQ5, DQ3 and DQ2. Figure 18.2, Figure 18.6, Figure

18.8 and Figure 18.9 show RY/BY# for read, reset, program, and erase operations, respectively.

Notes

1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See

Section 8.8.5, DQ5: Exceeded Timing Limits on page 35 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. See Section 8.8.1, DQ7: Data# Polling on page 31 and

Section 8.8.3, DQ2: Toggle Bit II on page 33 for further details.

Table 8.9 Write Operation Status

Operation

DQ7

(Note 2)

DQ6

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

RY/BY#

Standard

Mode

Embedded Program Algorithm

DQ7#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

Erase

Suspend

Mode

Reading within Erase

Suspended Sector

No toggle

N/A

Toggle

Reading within Non-Erase

Suspended Sector

Data

Erase-Suspend-Program

DQ7#

Toggle

N/A

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