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S29CD032J 数据表(PDF) 21 Page - SPANSION |
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S29CD032J 数据表(HTML) 21 Page - SPANSION |
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21 / 76 page ![]() September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 19 Da ta Shee t (Prelim i nar y ) 8. Device Operations This section describes the read, program, erase, simultaneous read/write operations, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command register (see Table 8.1). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine; the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command in order to return the device to the reading array data mode. 8.1 Device Operation Table The device must be set up appropriately for each operation. Table 8.1 describes the required state of each control pin for any particular operation. Legend L = Logic Low = VIL, H = Logic High = VIH, X = Don’t care. Notes 1. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block. 2. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB. Table 8.1 Device Bus Operation Operation CE# OE# WE# RESET# CLK ADV# Addresses Data (DQ0–DQ31) Read L L H H X X AIN DOUT Asynchronous Write L H L H X X AIN DIN Synchronous Write L H L H AIN DIN Standby (CE#) H X X H X X X HIGH Z Output Disable L H H H X X HIGH Z HIGH Z Reset X X X L X X X HIGH Z PPB Protection Status (Note 2) L L H H X X Sector Address, A9 = VID, A7 – A0 = 02h 00000001h, (protected) A6 = H 00000000h (unprotect) A6 = L Burst Read Operations Load Starting Burst Address L X H H AIN X Advance Burst to next address with appropriate Data presented on the Data bus L L H H H X Burst Data Out Terminate Current Burst Read Cycle H X H H X X HIGH Z Terminate Current Burst Read Cycle with RESET# XX H L X X X HIGH Z Terminate Current Burst Read Cycle; Start New Burst Read Cycle LH H H AIN X |
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