S29CD032J datasheet(23/76 Pages) SPANSION

23 / 76 page

September 27, 2006 S29CD-J_CL-J_00_B1

S29CD-J & S29CL-J Flash Family

Da ta

Shee t

(Prelim i nar y )

banks was in the middle of either a program or erase operation when RESET# was asserted, the user must

wait a period of tREADY before accessing that bank.

Asserting RESET# during a program or erase operation leaves erroneous data stored in the address

locations being operated on at the time of device reset. These locations need updating after the reset

operation is complete. See Section 18.4 for timing specifications.

Asserting RESET# active during VCC and VIO power-up is required to guarantee proper device initialization

until VCC and VIO have reached their steady state voltages. See Section 18.1.

8.4

Synchronous (Burst) Read Mode & Configuration Register

When a series of adjacent addresses need to be read from the device, the synchronous (or burst read) mode

can be used to significantly reduce the overall time needed for the device to output array data. After an initial

access time required for the data from the first address location, subsequent data is output synchronized to a

clock input provided by the system.

The device offers a linear method of burst read operation which is discussed in Section 8.4.1, 2-, 4-, 8-

Double Word Linear Burst Operation on page 22.

Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration

number of wait states to insert before the initial word (tIACC) of each burst access and when RDY indicates

that data is ready to be read. Prior to entering the burst mode, the system first determines the configuration

command sequence), then write the configuration register command sequence. See Section 8.4.3,

Configuration Register on page 24, and Table 20.1, Memory Array Command Definitions (x32 Mode)

on page 69 for further details. Once the configuration register is written to enable burst mode operation, all

subsequent reads from the array are returned using the burst mode protocols.

Figure 8.2 Synchronous/Asynchronous State Diagram

The device outputs the initial word subject to the following operational conditions:

tIACC specification: The time from the rising edge of the first clock cycle after addresses are latched to valid

data on the device outputs.

Configuration register setting CR13-CR10: The total number of clock cycles (wait states) that occur before

valid data appears on the device outputs. The effect is that tIACC is lengthened.

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Synchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(D15 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(D15 = 1)?

S29CD032J 数据表(PDF) 23 Page - SPANSION

S29CD032J 数据表(HTML) 23 Page - SPANSION

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