S29CD032J datasheet(22/76 Pages) SPANSION

22 / 76 page

S29CD-J & S29CL-J Flash Family

S29CD-J_CL-J_00_B1 September 27, 2006

Data

Sheet

(Pre limin ar y)

8.2

Asynchronous Read

All memories require access time to output array data. In an asynchronous read operation, data is read from

one memory location at a time. Addresses are presented to the device in random order, and the propagation

delay through the device causes the data on its outputs to arrive asynchronously with the address on its

inputs.

The internal state machine is set for asynchronously reading array data upon device power-up, or after a

hardware reset. This ensures that no spurious alteration of the memory content occurs during the power

transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles

that assert valid addresses on the device address inputs produce valid data on the device data outputs. The

device remains enabled for read access until the command register contents are altered.

The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the

power control and should be used for device selection (CE# must be set to VIL to read data). OE# is the

output control and should be used to gate data to the output pins if the device is selected (OE# must be set to

VIL in order to read data). WE# should remain at VIH (when reading data).

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output pins. The

output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output pins

(assuming the addresses have been stable for at least a period of tACC-tOE and CE# has been asserted for at

least tCE-tOE time). Figure 8.1 shows the timing diagram of an asynchronous read operation.

Figure 8.1 Asynchronous Read Operation

Note

Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.

Refer to Section 18.2, Asynchronous Operations on page 52 for timing specifications and to Figure 18.2,

Conventional Read Operations Timings on page 52 for another timing diagram. ICC1 in the DC

Characteristics table represents the active current specification for reading array data.

8.3

Hardware Reset (RESET#)

The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic “0”

on this input forces the device out of any mode that is currently executing back to the reset state. RESET#

may be tied to the system reset circuitry. A system reset would thus also reset the device. To avoid a potential

bus contention during a system reset, the device is isolated from the DQ data bus by tristating the data

outputs for the duration of the RESET pulse. All data outputs are “don’t care” during the reset operation.

If RESET# is asserted during a program or erase operation, the RY/BY# output remains low until the reset

operation is internally complete. The RY/BY# pin can be used to determine when the reset operation is

complete. Since the device offers simultaneous read/write operation, the host system may read a bank after a

period of tREADY2, if the bank was in the read/reset mode at the time RESET# was asserted. If one of the

CE#

CLK

ADV#

Addresses

Data

OE#

WE#

IND/WAIT#

VIH

Float

VOH

Address 0

Address 1

Address 2

Address 3

Float

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