ADN2806

Rev. 0 | Page 9 of 20

Table 6. Internal Register Map1

Reg

Name

R/W

Addr

D7

D6

D5

D4

D3

D2

D1

D0

FREQ0

R

0x0

MSB

LSB

FREQ1

R

0x1

MSB

LSB

FREQ2

R

0x2

0

MSB

LSB

MISC

R

0x4

x

x

x

Static

LOL

LOL

status

Data rate

measurement

complete

x

x

CTRLA

W

0x8

Measure data rate

Lock to reference

CTRLB

W

0x9

Config

LOL

Reset

MISC[4]

System

reset

0

Reset

MISC[2]

0

0

0

CTRLC

W

0x11

0

0

0

0

0

x

SQUELCH mode

Output boost

Table 7. Miscellaneous Register, MISC

Static LOL

LOL Status

Data Rate Measurement Complete

D7

D6

D5

D4

D3

D2

D1

D0

x

x

x

0 = Waiting for next LOL

0 = Locked

0 = Measuring data rate

x

x

1 = Static LOL until reset

1 = Acquiring

1 = Measurement complete

Table 8. Control Register, CTRLA1

Measure Data Rate

Lock to Reference

D7

D6

D5

D4

D3

D2

D1

D0

0

0

19.44 MHz

0

1

0

1

32

Set to 1 to measure data rate

0 = Lock to input data

0

1

38.88 MHz

0

1

0

1

32

1 = Lock to reference clock

1

0

77.76 MHz

0

1

0

1

32

1

1

155.52 MHz

0

1

0

1

32

REF

is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section).

Table 9. Control Register, CTRLB

Config LOL

Reset MISC[4]

System Reset

Reset MISC[2]

D7

D6

D5

D4

D3

D2

D1

D0

0 = LOL pin normal operation

1 = LOL pin is static LOL

Write a 1 followed

by 0 to reset MISC[4]

Write a 1 followed by

0 to reset ADN2806

Set to 0

Write a 1 followed

by 0 to reset MISC[2]

Set to 0

Set to 0

Set to 0

Table 10. Control Register, CTRLC

SQUELCH Mode

Output Boost

D7

D6

D5

D4

D3

D2

D1

D0

Set to 0

0 = Squelch data outputs and

clock outputs

0 = Default output swing

Set to 0

Set to 0

Set to 0

Set to 0

Set to 0

1 = Squelch data outputs or

clock outputs

1 = Boost output swing