ADN2806

Rev. 0 | Page 13 of 20

FUNCTIONAL DESCRIPTION

FREQUENCY ACQUISITION

The ADN2806 acquires frequency from the data. The lock

detector circuit compares the frequency of the VCO and the

frequency of the incoming data. When these frequencies differ

by more than 1000 ppm, LOL is asserted. This initiates a frequency

acquisition cycle. When the VCO frequency is within 250 ppm

of the data frequency, LOL is deasserted.

Once LOL is deasserted, the frequency-locked loop is turned

off. The PLL/DLL pulls the VCO frequency in the rest of the

way until the VCO frequency equals the data frequency.

The frequency loop requires a single external capacitor between

CF1 and CF2, Pin 14 and Pin 15. A 0.47 μF ± 20%, X7R ceramic

chip capacitor with <10 nA leakage current is recommended.

Leakage current of the capacitor can be calculated by dividing

the maximum voltage across the 0.47 μF capacitor, ~3 V, by the

insulation resistance of the capacitor. The insulation resistance

of the 0.47 μF capacitor should be greater than 300 MΩ.

INPUT BUFFER AMPLIFIER

The input buffer has differential inputs (PIN/NIN), which are

internally terminated with 50 Ω to an on-chip voltage reference

(VREF = 2.5 V typically). The minimum differential input level

LOCK DETECTOR OPERATION

The lock detector on the ADN2806 has three modes of

operation: normal mode, REFCLK mode, and static LOL mode.

Normal Mode

In normal mode, the ADN2806 is a CDR that locks onto a

622 Mbps data rate without the use of a reference clock as an

acquisition aid. In this mode, the lock detector monitors the

frequency difference between the VCO and the input data

frequency and deasserts the loss of lock signal, which appears

on Pin 16, LOL, when the VCO is within 250 ppm of the data

frequency. This enables the D/PLL, which pulls the VCO

frequency in the remaining amount and acquires phase lock.

Once locked, if the input frequency error exceeds 1000 ppm

(0.1%), the loss-of-lock signal is reasserted and control returns

to the frequency loop, which begins a new frequency

acquisition. The LOL pin remains asserted until the VCO locks

onto a valid input data stream to within 250 ppm frequency

error. This hysteresis is shown in Figure 15.

LOL

0

–250

250

1000

(ppm)

–1000

1

Figure 15. Transfer Function of LOL

LOL Detector Operation Using a Reference Clock

In REFCLK mode, a reference clock is used as an acquisition aid

to lock the ADN2806 VCO. Lock-to-reference mode is enabled

by setting CTRLA[0] to 1. The user also needs to write to the

CTRLA[7, 6] and CTRLA[5:2] bits to set the reference

frequency range and the divide ratio of the data rate with

respect to the reference frequency. For more details, see the

Reference Clock (Optional) section. In this mode, the lock

detector monitors the difference in frequency between the

divided down VCO and the divided down reference clock. The

loss-of-lock signal, which appears on Pin 16, LOL, is deasserted

when the VCO is within 250 ppm of the desired frequency. This

enables the D/PLL, which pulls the VCO frequency in the

remaining amount with respect to the input data and acquires

phase lock. Once locked, if the input frequency error exceeds

1000 ppm (0.1%), the loss-of-lock signal is reasserted and

control returns to the frequency loop, which reacquires with

respect to the reference clock. The LOL pin remains asserted

until the VCO frequency is within 250 ppm of the desired

frequency. This hysteresis is shown in Figure 15.

Static LOL Mode

The ADN2806 implements a static LOL feature that indicates if

a loss-of-lock condition has ever occurred. This feature remains

asserted, even if the ADN2806 regains lock, until the static LOL

LOL bit. If there is ever an occurrence of a loss-of-lock condition,

this bit is internally asserted to logic high. The MISC[4] bit remains

high even after the ADN2806 has reacquired lock to a new data

Register Bit CTRLB[6]. Once reset, the MISC[4] bit remains

deasserted until another loss-of-lock condition occurs.

Pin 16, to become a static LOL indicator. In this mode, the LOL

pin mirrors the contents of the MISC[4] bit and has the

functionality described in the previous paragraph. The CTRLB[7]

bit defaults to 0. In this mode, the LOL pin operates in the

normal operating mode, that is, it is asserted only when the

ADN2806 is in acquisition mode and deasserts when the

ADN2806 has reacquired lock.

SQUELCH MODES

Two modes for the SQUELCH pin are available with the

ADN2806: squelch data outputs and clock outputs mode and

squelch data outputs or clock outputs mode. Squelch data outputs

and clock outputs mode is selected when CTRLC[1] is 0 (default

mode). In this mode, when the SQUELCH input, Pin 27, is driven

to a TTL high state, both the data outputs (DATAOUTN and

DATAOUTP) and the clock outputs (CLKOUTN and CLKOUTP)

are set to the zero state to suppress downstream processing. If

the squelch function is not required, Pin 27 should be tied to VEE.