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ADN2806 数据表(PDF) 3 Page - Analog Devices

部件名 ADN2806
功能描述  622 Mbps Clock and Data Recovery IC
PDF  20 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADN2806 数据表(HTML) 3 Page - Analog Devices

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ADN2806
Rev. 0 | Page 3 of 20
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DATA INPUTS—DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN, dc-coupled
1.8
2.8
V
Peak-to-Peak Differential Input
PIN − NIN
0.2
2.0
V
Input Common-Mode Level
DC-coupled
2.3
2.5
2.8
V
DATA INPUTS—AC CHARACTERISTICS
Data Rate
622
Mbps
S11
@ 622 MHz
−15
dB
Output Clock Range
Absence of input data
622 ± 5%
MHz
Input Resistance
Differential
100
Ω
Input Capacitance
0.65
pF
LOSS-OF-LOCK (LOL) DETECT
VCO Frequency Error for LOL Assert
With respect to nominal
1000
ppm
VCO Frequency Error for LOL Deassert
With respect to nominal
250
ppm
LOL Response Time
OC-12
200
μs
ACQUISITION TIME
Lock to Data Mode
OC-12
2.0
ms
Optional Lock to REFCLK Mode
20.0
ms
DATA RATE READBACK ACCURACY
Fine Readback
In addition to REFCLK accuracy
OC-12
100
ppm
POWER SUPPLY VOLTAGE
3.0
3.3
3.6
V
POWER SUPPLY CURRENT
Locked to 622.08 Mbps
109
mA
OPERATING TEMPERATURE RANGE
–40
+85
°C
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer Bandwidth
OC-12
75
130
kHz
Jitter Peaking
OC-12
0
0.03
dB
Jitter Generation
OC-12, 12 kHz to 5 MHz
0.001
0.003
UI rms
0.011
0.026
UI p-p
Jitter Tolerance
OC-12, 223 − 1 PRBS
30 Hz1
100
UI p-p
300 Hz1
44
UI p-p
25 kHz
2.5
UI p-p
250 kHz1
1.0
UI p-p
1 Jitter tolerance of the ADN2806 at these jitter frequencies is better than what the test equipment is able to measure.



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