ADN2806

Rev. 0 | Page 15 of 20

REFERENCE CLOCK (OPTIONAL)

A reference clock is not required to perform clock and data

recovery with the ADN2806; however, support for an optional

reference clock is provided. The reference clock can be driven

differentially or in a single-ended fashion. If the reference

clock is not being used, REFCLKP should be tied to VCC, and

REFCLKN can be left floating or tied to VEE (the inputs are

internally terminated to VCC/2). See Figure 16 through Figure

18 for sample configurations.

The REFCLK input buffer accepts any differential signal with a

peak-to-peak differential amplitude of greater than 100 mV (for

example, LVPECL or LVDS) or a standard single-ended, low

voltage TTL input, providing maximum system flexibility.

Phase noise and duty cycle of the reference clock are not

critical, and 100 ppm accuracy is sufficient.

100kΩ

VCC/2

100kΩ

ADN2806

REFCLKP

10

11

REFCLKN

BUFFER

Figure 16. Differential REFCLK Configuration

100kΩ

VCC/2

100kΩ

ADN2806

REFCLKP

OUT

REFCLKN

BUFFER

VCC

CLK

OSC

Figure 17. Single-Ended REFCLK Configuration

100kΩ

VCC/2

100kΩ

ADN2806

REFCLKP

10

11

NC

REFCLKN

BUFFER

VCC

Figure 18. No REFCLK Configuration

There are two mutually exclusive uses, or modes, of the

reference clock. The reference clock can be used either to help

the ADN2806 lock onto data or to measure the frequency of the

incoming data to within 0.01%. The modes are mutually

exclusive because in the first use the user knows exactly what

the data rate is and wants to force the part to lock onto only that

data rate, and in the second use the user does not know what

the data rate is and wants to measure it.

Bit CTRLA[0]. Fine data rate readback mode is enabled by

these bits at the same time causes an indeterminate state and is

not supported.

Using the Reference Clock to Lock onto Data

In this mode, the ADN2806 locks onto a frequency derived

from the reference clock according to

The user must provide a reference clock that is a function of the

data rate. By default, the ADN2806 expects a reference clock of

19.44 MHz. Other options are 38.88 MHz, 77.76 MHz, and

155.52 MHz, which are selected by programming CTRLA[7, 6].

CTRLA[5:2] should be programmed to [0101] for all cases.

Table 11. CTRLA Settings

CTRLA[7, 6]

Range (MHz)

CTRLA[5:2]

Ratio

00

19.44

0101

01

38.88

0101

10

77.76

0101

11

155.52

0101

For example, if the reference clock frequency is 38.88 MHz and the

input data rate is 622.08 Mbps, CTRLA[7, 6] is set to [01] to

produce a divided-down reference clock of 19.44 MHz, and

CTRLA[5:2] is set to [0101], that is, 5, because

In this mode, if the ADN2806 loses lock for any reason, it relocks

onto the reference clock and continues to output a stable clock.

While the ADN2806 is operating in lock-to-reference mode,

a 0 to 1 transition should be written into the CTRLA[0] bit to

initiate a lock-to-reference clock command.