ADN2806

Rev. 0 | Page 17 of 20

APPLICATIONS INFORMATION

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. The

VEE pins should be soldered directly to the ground plane to

reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance, especially on Pin 23, which is the ground return for

the output buffers. The exposed pad should be connected to the

GND plane using plugged vias so that solder does not leak

through the vias during reflow.

Use of a 22 μF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they

should be placed between ADN2806 supply pins VCC and VEE,

as close as possible to the ADN2806 VCC pins.

If connections to the supply and ground are made through

vias, the use of multiple vias in parallel helps to reduce series

inductance, especially on Pin 24, which supplies power to the

high speed CLKOUTP/CLKOUTN and DATAOUTP/

DATAOUTN output buffers. Refer to Figure 19 for the

recommended connections.

By placing the power supply and GND planes adjacent to each

other and using close spacing between the planes, excellent high

frequency decoupling can be realized. The capacitance is given

by

( )

pF

/

0.88ε

r

d

A

C

where:

ε

r

is the dielectric constant of the PCB material.

d is the separation between planes (mm).

50Ω TRANSMISSION LINES

DATAOUTP

DATAOUTN

CLKOUTP

CLKOUTN

0.1µF

22µF

1nF

0.1µF

0.1µF

0.1µF

1.6µF

1.6µF

0.1µF

0.47µF ±20%

>300MΩ INSULATION RESISTANCE

1nF

1nF

1nF

0.1µF

1nF

+

VCC

50Ω

50Ω

LIM

VCC

µC

µC

VCC

VCC

1

TEST1

2

VCC

3

VREF

4

NIN

5

PIN

6

NC

7

NC

8

VEE

24

VCC

23

VEE

22

NC

21

SDA

20

SCK

19

SADDR5

18

VCC

17

VEE

EXPOSED PAD

TIED OFF TO

VEE PLANE

WITH VIAS

Figure 19. Typical ADN2806 Applications Circuit