ADP1821

Rev. B | Page 10 of 24

When the ADP1821 senses an overcurrent condition, the next

switching cycle is suppressed, the soft start capacitor is discharged

through an internal 2.5 kΩ resistor, and the error amplifier

output voltage is pulled down. The ADP1821 remains in this

mode for as long as the overcurrent condition persists. When

the overcurrent condition is removed, operation resumes in soft

start mode.

See the Setting the Current Limit section for more information.

MOSFET DRIVERS

The DH pin drives the high-side switch MOSFET. This is a

boosted 5 V gate driver that is powered by a bootstrap capaci-

tor circuit. This configuration allows the high-side, N-channel

MOSFET gate to be driven above the input voltage, allowing full

enhancement and a low voltage drop across the MOSFET. The

bootstrap capacitor is connected from the SW pin to the BST

pin. A bootstrap Schottky diode connected from the PVCC pin

to the BST pin recharges the bootstrap capacitor every time the

SW node goes low. Use a bootstrap capacitor value greater than

100× the high-side MOSFET input capacitance.

In practice, the switch node can run up to 24 V of input voltage,

and the boost nodes can operate more than 5 V above this to

allow full gate drive. The power input voltage can be run from

1 V to 24 V.

The switching cycle is initiated by the internal clock signal. The

high-side MOSFET is turned on by the DH driver, and the SW

node goes high, pulling up on the inductor. When the internally

generated ramp signal crosses the COMP pin voltage, the switch

MOSFET is turned off and the low-side synchronous rectifier

MOSFET is turned on by the DL driver. Active break-before-

make circuitry as well as a supplemental fixed dead time are

used to prevent cross-conduction in the switches.

The DL pin provides the gate drive for the low-side MOSFET

synchronous rectifier. Internal circuitry monitors the external

MOSFETs to ensure break-before-make switching to prevent

cross-conduction. An active dead-time reduction circuit

reduces the break-before-make time of the switching to limit

the losses due to current flowing through the synchronous

rectifier body diode.

The PVCC pin provides power to the low-side drivers. It is

limited to 5.5 V maximum input and should have a local

decoupling capacitor to PGND.

The synchronous rectifier is turned on for a minimum time

of about 200 ns on every switching cycle in order to sense the

current. This and the nonoverlap dead time put a limit on the

maximum high-side switch duty cycle based on the selected

switching frequency. Typically, this is about 90% at 300 kHz

switching, and at 1 MHz switching, it reduces to about 70%

maximum duty cycle.

INPUT VOLTAGE RANGE

The ADP1821 takes its internal power from the VCC and PVCC

inputs. PVCC powers the low-side MOSFET gate drive (DL),

and VCC powers the internal control circuitry. Both of these

inputs are limited to between 3.0 V and 5.5 V. Bypass PVCC to

PGND with a 1 μF or greater capacitor. Bypass VCC to GND

with a 0.1 μF or greater capacitor.

The power input to the dc-to-dc converter can range between

1.2× the output voltage and 24 V. Bypass the power input to

PGND with a suitably large capacitor. See the Selecting the

Input Capacitor section.

SETTING THE OUTPUT VOLTAGE

The output voltage is set using a resistive voltage divider from

the output to FB. The voltage divider drops the output voltage

to the 0.6 V FB regulation voltage to set the regulation output

voltage. The output voltage is set to voltages as low as 0.6 V and

as high as 85% of the minimum power input voltage (see the

Feedback Voltage Divider section).

SWITCHING FREQUENCY CONTROL AND

SYNCHRONIZATION

The ADP1821 has a logic-controlled frequency select input (FREQ)

which sets the switching frequency to 300 kHz or 600 kHz. Drive

FREQ low for 300 kHz and high for 600 kHz.

The SYNC input is used to synchronize the converter switching

frequency to an external signal. The converter switching can be

synchronized to an external signal. This allows multiple ADP1821

converters to be operated at the same frequency to prevent

frequency beating or other interactions.

To synchronize the ADP1821 switching to an external signal,

drive the SYNC input with a synchronizing signal. The ADP1821

can only synchronize up to 2× the nominal oscillator frequency.

If the frequency is set to 300 kHz (FREQ connected to GND),

then the synchronization frequency needs to be in between

300 kHz and 600 kHz. Since the 300 kHz setting has a mini-

mum specification (see Table 1) of 250 kHz and a maximum

of 375 kHz over the specified temperature range, the recom-

mended synchronization frequency range is between 375 kHz

and 500 kHz to cover the whole range of part-to-part variation

and over the operating temperature range. If the frequency is set

to 600 kHz (FREQ connected to VCC), then the synchronization

frequency needs to be in between 600 kHz and 1.2 MHz. Since

the 600 kHz setting has a minimum specification (see Table 1)

of 470 kHz and a maximum of 720 kHz over the specified tem-

perature range, the recommended synchronization frequency

range is between 720 kHz and 940 kHz to cover the whole range

of part-to-part variation and over the operating temperature

range. Driving SYNC faster than recommended for the FREQ

setting results in a small ramp signal, which could affect the

signal-to-noise ratio and the modulator gain and stability.