ADP1821ARQZ-R7 datasheet(15/24 Pages) AD

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ADP1821

Rev. B | Page 15 of 24

Generally speaking, the LC corner frequency is about two

orders of magnitude below the switching frequency, and

therefore about one order of magnitude below crossover.

To achieve sufficient phase margin at crossover to guarantee

stability, the design must compensate for the two poles at the

LC corner frequency with two zeros to boost the system phase

prior to crossover. The two zeros require an additional pole or

two above the crossover frequency to guarantee adequate gain

margin and attenuation of switching noise at high frequencies.

Depending on component selection, one zero might already be

generated by the ESR of the output capacitor. Calculate this zero

corner frequency, fESR, as

OUT

ESR

(19)

This zero is often near or below crossover and is useful in

bringing back some of the phase lost at the LC corner.

Figure 15 shows a typical bode plot of the LC filter by itself.

0dB

GAIN

FREQUENCY

LC FILTER BODE PLOT

PHASE

fLC

fESR

fCO

fSW

AFILTER

–40dB/dec

ΦFILTER

0°

–90°

–180°

–20dB/dec

Figure 15. LC Filter Bode Plot

The gain of the LC filter at crossover can be linearly

approximated from Figure 15 as

ESR

FILTER

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

ESR

FILTER

log

(20)

If fESR ≈ fCO, then add another 3 dB to account for the local

difference between the exact solution and the preceding linear

approximation.

To compensate the control loop, the gain of the system must

be brought back up so that it is 0 dB at the desired crossover

frequency. Some gain is provided by the PWM modulation

itself, so next calculate

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

RAMP

MOD

log

(21)

For systems using the internal oscillator, this becomes

⎟

⎠

⎞

⎜

⎝

⎛

log

MOD

(22)

Note that if the converter is being synchronized, the ramp

voltage, VRAMP, is lower than 1.25 V by the percentage of

frequency increase over the nominal setting of the FREQ pin:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

SYNC

FREQ

RAMP

(23)

The rest of the system gain needed to reach 0 dB at crossover is

provided by the error amplifier and is covered in the compen-

sation design information that follows. The total gain of the

system therefore, is given by

AT = AMOD + AFILTER + ACOMP

(24)

where:

AMOD

is the gain of the PWM modulator

AFILTER

is the gain of the LC filter including the effects of the

ESR zero

ACOMP

is the gain of the compensated error amplifier.

Additionally, the phase of the system must be brought back up

to guarantee stability. Note from the bode plot of the filter that

the LC contributes −180 degrees of phase shift. Additionally,

because the error amplifier is an integrator at low frequency,

it contributes an initial −90 degrees. Therefore, before adding

compensation or accounting for the ESR zero, the system is

already down −270 degrees. To avoid loop inversion at cross-

over, or −180 degrees phase shift, a good initial practical design

is to require a phase margin of 60 degrees, which is therefore an

overall phase loss of −120 degrees from the initial low frequency

dc phase. The goal of the compensation is to boost the phase

back up from −270 degrees to −120 degrees at crossover.

Two common compensation schemes are used, which are

sometimes referred to as Type II or Type III compensation,

depending on whether the compensation design includes

two or three poles. (Dominant pole compensations, or single

pole compensation, is referred to as Type I compensation, but

unfortunately it is not very useful for dealing successfully with

switching regulators.)

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