ADP1821

Rev. B | Page 14 of 24

SETTING THE CURRENT LIMIT

The current limit comparator measures the voltage across the

low-side MOSFET to determine the load current.

equal to or greater than this offset voltage, the ADP1821 flags

a current-limit event.

and temperature, the minimum current limit should be set to

ensure that the system can handle the maximum desired load

current. To do this, use the peak current in the inductor, which

is the desired current-limit level plus the ripple current, the

perature, and the minimum CSL current.

μA

42

)

(MAX

DSON

LPK

CL

R

I

R

=

(15)

When an over-current event occurs, the over-current compara-

tor does prevent switching cycles until the rectifier current has

decayed below the threshold. The over-current comparator is

blanked for the first 100 ns of the synchronous rectifier cycle to

prevent switch node ringing from falsely tripping the current

limit. The ADP1821 senses the current limit during the off

cycle. When the current limit condition occurs, the ADP1821

resets the internal clock until the over-current condition

disappears. This suppresses the start clock cycles until the

overload condition is removed. At the same time, the SS cap

is discharged through a 2.5 kΩ resistor. The SS input is an

auxiliary positive input of the error amplifier, so it behaves

like another voltage reference. The lowest reference voltage

wins. Discharging the SS voltage causes the converter to use

a lower voltage reference when switching is allowed again.

Therefore, as switching cycles continue around the current

limit, the output looks roughly like a constant current source

due to the rectifier limit, and the output voltage droops as the

load resistance decreases. When the overload condition is

removed, the output recovers with the normal soft start slope

and does not overshoot.

Because the buck converter is usually running at a fairly high

current, PCB layout and component placement may affect

required for a particular board layout and MOSFET selection.

If alternate MOSFETs are substituted at some point in production,

FEEDBACK VOLTAGE DIVIDER

The output regulation voltage is set through the feedback

voltage divider. The output voltage is reduced through the

voltage divider and drives the FB feedback input. The regula

tion threshold at FB is 0.6 V. The maximum input bias current

into FB is 100 nA. For a 0.15% degradation in regulation voltage

to be less than 9 kΩ, which results in 67 μA of divider current.

but results in a reduction in output voltage accuracy due to the

input bias current at the FB pin, while lower values cause increased

voltage by using the following equation:

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

=

FB

FB

OUT

BOT

TOP

V

V

V

R

R

_

(16)

where:

is the high-side voltage divider resistance.

is the low-side voltage divider resistance.

is the regulated output voltage.

is the feedback regulation threshold, 0.6 V.

COMPENSATING THE VOLTAGE MODE BUCK

REGULATOR

Assuming the LC filter design is complete, the feedback control

system can then be compensated. Good compensation is critical

to proper operation of the regulator. Calculate the quantities in

Equation 17 through Equation 58 to derive the compensation

values. For convenience, a summary of the design equations is

located in the Summary of Equations section. The information

can then be added to an Excel spreadsheet, for automated

calculation.

The goal is to guarantee that the voltage gain of the buck con-

verter crosses unity at a slope that provides adequate phase

margin for stable operation. Additionally, at frequencies

gain margin and attenuation of switching noise are important

secondary goals. For initial practical designs, a good choice for

the crossover frequency is one tenth of the switching frequency;

so first calculate

10

SW

CO

f

f

=

(17)

This gives sufficient frequency range to design a compensation

that attenuates switching artifacts, while also giving sufficient

control loop bandwidth to provide good transient response.

The output LC filter is a resonant network that inflicts two poles

LC

π

f

LC

2

1

=

(18)