ADP1821

Rev. B | Page 21 of 24

APPLICATION CIRCUITS

The ADP1821 controller can be configured to regulate an output

with a load of more than 20 A if the power components, such

as the inductor, MOSFETs, and the bulk capacitors, are chosen

carefully to meet the power requirement. The maximum load

and power dissipation are limited by the power-train compo-

nents. Figure 1 shows a typical application circuit that can drive

an output load of 20 A. Note that two low-side MOSFETs are

needed to deliver the 20 A load. In this example, two power rails

are needed: a 5 V bias supply, which needs to supply about 30

mA to power the ADP1821 at full load, and a power input rail,

which ranges from 2.5 V to 20 V. The bulk input and output

tors, which have low ESR and high-current ripple rating. An

alternative to the OSCON capacitors are the polymer aluminum

capacitors that are available from other manufacturers such as

United Chemi-Con. Aluminum electrolytic capacitors, such as

Rubycon’s ZLG low-ESR series, can also be paralleled up at the

input or output to meet the current ripple requirement. Since

the aluminum electrolytic capacitors have higher ESR and much

larger variation in capacitance over the operating temperature

range, a larger bulk input and output capacitance is needed to

reduce the effective ESR and suppress the current ripple.

The ADP1821 can be configured to drive an output load of

less than 1 A. Figure 21 shows a typical application circuit that

drives a 3 A load in an all multilayer ceramic capacitor (MLCC)

solution. Notice that the two MOSFETs used in this example are

dual-channel MOSFETs in a PowerPAK® SO-8 package, which

reduces cost and saves layout space. For input voltages less than

3.7 V, it is recommended to use MOSFETs that are fully turned

drop across the Schottky diode D1, for input voltages less than

3.3 V, the effective voltage to the internal gate drivers may not

be enough to drive a large load at the output. A Schottky diode

input voltages less than 3.3 V.

GND

PVCC

ADP1821

SHDN

VCC

BST

DH

SW

CSL

DL

PGND

FB

FREQ

SYNC

PWGD

COMP

SS

1µF

1µF

10Ω

2kΩ

4.1kΩ

84.5Ω

1kΩ

100kΩ

M1

M2

L1 = 2.2µH

OUTPUT

1.8V, 3A

VIN = 3V TO 5.5V

D1

AGND

100nF

6.65kΩ

1.5nF

120pF

0.22µF

+

1µF

10V

+

10µF

10V

×2

1µF

10V

47µF

6.3V

100µF

6.3V

8.2nF

M1, M2: VISHAY, DUAL-CHANNEL MOSFET Si7940DP

L1: TOKO, FDV0620-2R2M

D1: CENTRAL SEMI, CMDSH2-4L

Figure 21. Typical Application Circuit with all Multilayer Ceramic Capacitors (MLCC), 3.3 V to 5 V Input