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ES9822PRO 数据表(PDF) 48 Page - ESS Technology,Inc

部件名 ES9822PRO
功能描述  32-bit High-Performance 2-Channel ADC
PDF  126 Pages
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制造商  ESS [ESS Technology,Inc]
网页  http://www.esstech.com
标志 ESS - ESS Technology,Inc

ES9822PRO 数据表(HTML) 48 Page - ESS Technology,Inc

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ES9822 PRO Product Datasheet
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
48
Register 1: ADC CLOCK CONFIG1
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
Bits
Mnemonic
Description
[7]
ENABLE_DATA_IN_CH2B
Enables Ch2B data input clock (before decimation path) for
data mixing.
1'b0: Clock disabled (default)
1'b1: Clock enabled
[6]
ENABLE_DATA_IN_CH1B
Enables Ch1B data input clock (before decimation path) for
data mixing.
1'b0: Clock disabled (default)
1'b1: Clock enabled
[5]
ENABLE_DATA_IN_CH2A
Enables Ch2A data input clock (before decimation path) for
data mixing.
1'b0: Clock disabled (default)
1'b1: Clock enabled
[4]
ENABLE_DATA_IN_CH1A
Enables Ch1A data input clock (before decimation path) for
data mixing.
1'b0: Clock disabled (default)
1'b1: Clock enabled
[3]
ENABLE_ADC_CH2B
Enables ADC Ch2B decimation path clock.
1'b0: Clock disabled (default)
1'b1: Clock enabled
[2]
ENABLE_ADC_CH1B
Enables ADC Ch1B decimation path clock.
1'b0: Clock disabled (default)
1'b1: Clock enabled
[1]
ENABLE_ADC_CH2A
Enables ADC Ch2A decimation path clock.
1'b0: Clock disabled (default)
1'b1: Clock enabled
[0]
ENABLE_ADC_CH1A
Enables ADC Ch1A decimation path clock.
1'b0: Clock disabled (default)
1'b1: Clock enabled



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