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ES9822PRO 数据表(PDF) 95 Page - ESS Technology,Inc |
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ES9822PRO 数据表(HTML) 95 Page - ESS Technology,Inc |
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95 / 126 page  0.3 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 95 ES9822 PRO Product Datasheet ADC CH2 Registers Register 118: ADC CH2 DATAPATH CONTROL Bits [7] [6] [5:3] [2] [1] [0] Default 1'b0 1'b0 3'b000 1'b0 1'b0 1'b0 Bits Mnemonic Description [7] ADC2_BYPASS_FIR2X • 1'b0: Non-bypass (default) • 1'b1: Bypass DFir_2x [6] ADC2_BYPASS_FIR4X • 1'b0: Non-bypass (default) • 1'b1: Bypass DFir_4x [5:3] RESERVED NA [2] ADC2_ENABLE_DC_BLOCKING Enables DC blocking path. • 1'b0: Disabled (default) • 1'b1: Enabled [1] RESERVED NA [0] ADC2_NEG_SEL Negates data input from analog ADC. • 1'b0: No negation (default) • 1'b1: Negates input data Register 119: ADC CH2 THD COMP CONFIG Bits [7:2] [1] [0] Default 6'd0 1'b0 1'b0 Bits Mnemonic Description [7:2] ADC2_CORRECTION_ADDR Selects the address when writing the THD compensation RAM. [1] ADC2_CORRECTION_WE Enables writing to the THD compensation RAM. • 1'b0: Writing disabled (default) • 1'b1: Writing enabled [0] ADC2_ENABLE_THD_COMP Selects whether THD compensation is enabled and used in the signal path, or disabled and bypassed. • 1'b0: THD compensation is disabled and bypassed (default) • 1'b1: THD compensation is enabled. Data is processed by THD compensation Register 121-120: ADC CH2 THD COMP DATA Bits [15:0] Default 16'd0 Bits Mnemonic Description [15:0] ADC2_CORRECTION_DATA A 16 bits THD corrected value that will be written to the address of the THD compensation RAM. Maximum -42dB (16'hFFFF). |
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