AT89LP4052-20PI datasheet(13/90 Pages) ATMEL

13 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

13. Interrupts

The AT89LP2052/LP4052 provides 6 interrupt sources: two external interrupts, two timer inter-

rupts, a serial port interrupt, and an analog comparator interrupt. These interrupts and the

system reset each have a separate program vector at the start of the program memory space.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the

interrupt enable register IE. The IE register also contains a global disable bit, EA, which disables

all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or

clearing bits in the interrupt priority registers IP and IPH. An interrupt service routine in progress

can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower

priority. The highest priority interrupt cannot be interrupted by any other interrupt source. If two

requests of different priority levels are pending at the end of an instruction, the request of higher

priority level is serviced. If requests of the same priority level are pending at the end of an

instruction, an internal polling sequence determines which request is serviced. The polling

sequence is based on the vector address; an interrupt with a lower vector address has higher

priority than an interrupt with a higher vector address. Note that the polling sequence is only

used to resolve pending requests of the same priority level.

The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated,

depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these inter-

rupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears

the flag that generated an external interrupt only if the interrupt was edge-activated. If the inter-

rupt was level activated, then the external requesting source (rather than the on-chip hardware)

controls the request flag.

Table 12-1.

PCON

– Power Control Register

PCON = 87H

Reset Value = 000X 0000B

Not Bit Addressable

SMOD1

SMOD0

PWDEX

POF

GF1

GF0

IDL

Bit

543

Symbol

Function

SMOD1

Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.

SMOD0

Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after

a frame error regardless of the state of SMOD0.

PWDEX

Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 0, wake

up from Power-down is internally timed.

POF

Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not

affected by RST or BOD (i.e. warm resets).

GF1, GF0

General-purpose Flags

Power-down bit. Setting this bit activates power-down operation.

IDL

Idle Mode bit. Setting this bit activates Idle mode operation

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