AT89LP4052-20PI datasheet(46/90 Pages) ATMEL

46 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

19. Analog Comparator

A single analog comparator is provided on the AT89LP2052/LP4052. Comparator operation is

such that the output is a logic “1” when the positive input AIN0 (P1.0) is greater than the negative

input AIN1 (P1.1). Otherwise, the output is a zero. Setting the CEN bit in ACSR enables the

comparator. When the comparator is first enabled, the comparator output and interrupt flag are

guaranteed to be stable only after 10 µs. The corresponding comparator interrupt should not be

enabled during that time, and the comparator interrupt flag must be cleared before the interrupt

is enabled in order to prevent an immediate interrupt service. Before enabling the comparator

the analog inputs should be tri-stated by putting P1.0 and P1.1 into input-only mode. See Sec-

tion 14.5 “Port 1 Analog Functions” on page 19.

The comparator output is internally tied to the P3.6 pin. Instructions which read the pins of P3

will also read the comparator output directly. Read-Modify-Write instructions or Write instructions

to P3.6 will access bit 6 of the Port 3 register without affecting the comparator.

The comparator may be configured to cause an interrupt under a variety of output value condi-

tions by setting the CM bits in ACSR. The comparator interrupt flag CF in ACSR is set whenever

the comparator output matches the condition specified by CM. The flag may be polled by soft-

ware or may be used to generate an interrupt and must be cleared by software. The EC bit in IE

must be set before CF will generate an interrupt.

19.1

Comparator Interrupt with Debouncing

The comparator output is sampled every clock cycle. The conditions on the analog inputs may

be such that the comparator output will toggle excessively. This is especially true if applying slow

moving analog inputs. Three debouncing modes are provided to filter out this noise. In debounc-

ing mode, the comparator uses Timer 1 to modulate its sampling time. When a relevant

transition occurs, the comparator waits until two Timer 1 overflows have occurred before resam-

pling the output. If the new sample agrees with the expected value, CF is set. Otherwise the

event is ignored. The filter may be tuned by adjusting the time-out period of Timer 1. Because

Timer 1 is free running, the debouncer must wait for two overflows to guarantee that the sam-

pling delay is at least 1 time-out period. Therefore after the initial edge event, the interrupt may

occur between 1 and 2 time-out periods later. See Figure 19-1.

By default the comparator is disabled during Idle mode. To allow the comparator to function dur-

ing Idle, the CIDL bit in ACSR must be set. When CIDL is set, the comparator can be used to

wake-up the CPU from Idle if the comparator interrupt is enabled. The comparator is always dis-

abled during Power-down mode.

Figure 19-1. Negative Edge with Debouncing Example

Comparator Out

Timer 1 Overflow

Start

Compare

Start

Compare

AT89LP4052-20PI 数据表(PDF) 46 Page - ATMEL Corporation

AT89LP4052-20PI 数据表(HTML) 46 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载