AT89LP4052-20PI datasheet(24/90 Pages) ATMEL

24 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

Table 15-1.

TCON

– Timer/Counter Control Register

TMOD = 88H

Reset Value = 0000 0000B

Not Bit Addressable

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

Symbol

Function

TF1

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to

interrupt routine.

TR1

Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off.

TF0

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to

interrupt routine.

TR0

Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off.

IE1

Interrupt 1 flag. When IT1 is set, IE1 is set by hardware when the external interrupt falling edge is detected, and is cleared

by hardware when the CPU vectors to the interrupt routine. When IT1 is cleared, IE1 is sampled and inverted from the

external interrupt pin. The flag will be set or cleared by hardware depending on the state of P3.3.

IT1

Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

IE0

Interrupt 0 flag. When IT0 is set, IE0 is set by hardware when the external interrupt falling edge is detected, and is cleared

by hardware when the CPU vectors to the interrupt routine. When IT0 is cleared, IE0 is sampled and inverted from the

external interrupt pin. The flag will be set or cleared by hardware depending on the state of P3.2.

IT0

Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

AT89LP4052-20PI 数据表(PDF) 24 Page - ATMEL Corporation

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