AT89LP4052-20PI datasheet(27/90 Pages) ATMEL

27 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

Figure 15-6. Timer/Counter 1 PWM Mode 0

Figure 15-7. Timer/Counter 1 PWM Mode 1

15.6

Timer/Counter Pin Configuration

In order to use the counter input function or pulse width modulation output feature of Timer 0 or

Timer 1, the Timer pins T0 (P3.4) and T1 (P3.5) must be configured appropriately. See Section

14.7 “Port Alternate Functions” on page 20. For the external counter input function, T0 or T1

should be configured as input-only, or as bidirectional with P3.4 or P3.5 set to “1”. The counter

function may also be triggered by an internal event if T0 or T1 is configured in a bidirectional or

output mode and the port bit is toggled accordingly. To enable a PWM output on T0 or T1, the

pin must be configured in a bidirectional or output mode with P3.4 or P3.5 set to “1”. Setting the

PWM0EN or PWM1En bits in TCONB will not automatically configure the pins as outputs. The

PWM outputs will use a full CMOS push-pull driver if they are in the quasi-bidirectional or output

configurations.

16. External Interrupts

The INT0 and INT1 external interrupt sources can be programmed to be level-activated or tran-

sition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external

interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is nega-

tive edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle

OSC

TR1

GATE

INT1 Pin

TL1

(8 Bits)

Control

PSC1

TH1

(8 Bits)

OCR1

RH1

(8 Bits)

OSC

TR1

GATE

INT1 Pin

TL1

(8 Bits)

Control

TH1

(8 Bits)

OCR1

RH1

(8 Bits)

RL1

(8 Bits)

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