AT89LP4052-20PI datasheet(39/90 Pages) ATMEL

39 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

Slave 0

SADDR = 1100 0000

SADEN = 1111 1001

Given

= 1100 0XX0

Slave 1

SADDR = 1110 0000

SADEN = 1111 1010

Given

= 1110 0X0X

Slave 2

SADDR = 1110 0000

SADEN = 1111 1100

Given

= 1110 00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave

0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit

1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its

unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2, use address 1110

0100, since it is necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN.

Zeros in this result are treated as don’t cares. In most cases, interpreting the don’t cares as

ones, the broadcast address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with

“0”s. This produces a given address of all “don’t cares” as well as a Broadcast address of all

“don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcon-

troller to use standard 80C51-type UART drivers which do not make use of this feature.

18. Serial Peripheral Interface

The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the

AT89LP2052/LP4052 and peripheral devices or between multiple AT89LP2052/LP4052

devices. The AT89LP2052/LP4052 SPI features include the following:

• Full-duplex, 3-wire Synchronous Data Transfer

• Master or Slave Operation

• Maximum Bit Frequency = f/4

• LSB First or MSB First Data Transfer

• Four Programmable Bit Rates in Master Mode

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Double-buffered Receive

• Double-buffered Transmit (Enhanced Mode Only)

• Wake up from Idle Mode (Slave Mode Only)

The interconnection between master and slave CPUs with SPI is shown in Figure 18-1. The four

pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock

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