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Am29BDS643G

25692A2 May 8, 2006

D A TA

SH EE T

AC CHARACTERISTICS

Notes:

1. Figure shows total number of clock cycles set to four.

2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency

is not present if PS is not enabled.

3. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and are indicated by RDY.

Figure 10.

Burst Mode Read (40 MHz)

Da

Da + 1

Da + 2

Da + n

OE#

A/DQ0:

A/DQ15

A16:

A21

Aa

AVD#

RDY

CLK

CE#

Aa

4 cycles for initial access shown.

Programmable wait state function is set to 02h.

1 cycle

wait state

when PS

enabled

25 ns typ.

Hi-Z

Hi-Z

Hi-Z