May 8, 2006 25692A2

Am29BDS643G

43

D A TA

SH EE T

AC CHARACTERISTICS

Note: Devices should be programmed with wait states as discussed in the “Programmable Wait State” section on page 10.

Figure 20.

Initial Access with Power Saving (PS) Function and Address Boundary Latency

Figure 21.

Example of Extended Valid Address Reducing Wait State Usage

CLK

AVD#

RDY

PS

Address

High-Z

High-Z

A/DQ0:

A/DQ15

PS

OE#

D0

D1

D2

PS1

PS2

device is programmable from 2 to 7 total cycles

during initial access (here, programmable wait state

function is set to 04h; 6 cycles total)

PS high if data is inverted,

low if data is not inverted

2 additional

wait states if

address is

at boundary

1 additional

wait state to

indicate PS

is enabled

AVD# low with clock

present enables

burst read mode

Address

A16:A21

boundary

latency

CLK

AVD#

RDY

High-Z

A/DQ

OE#

CE#

D0

D1

D2

Addresses