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AM29BDS643G 数据表(PDF) 44 Page - Advanced Micro Devices |
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AM29BDS643G 数据表(HTML) 44 Page - Advanced Micro Devices |
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44 / 49 page ![]() 42 Am29BDS643G 25692A2 May 8, 2006 D A TA SH EE T AC CHARACTERISTICS Note: 8-word linear burst mode shown. 16- and 32-word linear burst read modes behave similarly. Figure 18. 8-, 16-, and 32-Word Linear Burst Address Wrap Around Note: Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure 19. Latency with Boundary Crossing (54 MHz and 66 MHz) CLK Address (hex) D0 D1 D2 A/DQ0: A/DQ15 OE#, CE# Address wraps back to beginning of address group. 39 39 3A 3B 3C 3D 3E 3F 38 Initial Access VIL VIH AVD# VIL VIH D3 D4 D5 D6 D7 CLK Address (hex) C59 C60 C61 C62 C62 C62 C63 C64 C65 C66 D59 D60 D61 D62 D63 D64 D65 D66 (stays high) AVD# RDY A/DQ0: A/DQ15 OE#, CE# (stays low) Address boundary occurs every 64 words, beginning at address 00003Eh: 00007Eh, 0000BEh, etc. Address 000000h is also a boundary crossing. 3B 3C 3D 3E 3E 3E 3F 40 41 42 latency tRACC |
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