AM29LV640MT110REF datasheet(31/66 Pages) AMD

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February 1, 2007 26190C8

Am29LV640MT/B

D A TA

SH EET

Word/Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Tables 12 and 13 show the

address and data requirements for the word program

command sequence. Note that the autoselect and CFI

functions are unavailable when a program operation is

in progress.

When the Embedded Program algorithm is complete,

the device then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7 or DQ6. See Write Operation Status on page 38

for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once the device has returned to the read

mode, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so can

cause the device to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read shows that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram words to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Tables 12 and 13 show the requirements

for the command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h. The second cycle must contain the data 00h. The

device then returns to the read mode.

Write Buffer Programming

Write Buffer Programming allows the system write to a

maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming

time than the standard programming algorithms. The

Write Buffer Programming command sequence is initi-

ated by first writing two unlock cycles. This is followed

by a third write cycle containing the Write Buffer Load

command written at the Sector Address in which pro-

gramming occurs. The fourth cycle writes the sector

address and the number of word locations, minus one,

to be programmed. For example, if the system pro-

grams six unique address locations, then 05h should

be written to the device. This tells the device how

many write buffer addresses are loaded with data and

therefore when to expect the Program Buffer to Flash

command. The number of locations to program cannot

exceed the size of the write buffer or the operation

aborts.

The fifth cycle writes the first address location and

data to be programmed. The write-buffer-page is se-

lected by address bits A

MAX–A4. All subsequent ad-

dr ess/ dat a

p a ir s

m u s t

f a ll

within

th e

selected-write-buffer-page. The system then writes the

remaining address/data pairs into the write buffer.

Write buffer locations can be loaded in any order.

The write-buffer-page address must be the same for

all address/data pairs loaded into the write buffer.

(This means Write Buffer Programming cannot be per-

formed across multiple write-buffer pages. This also

means that Write Buffer Programming cannot be per-

formed across multiple sectors. If the system attempts

to load programming data outside of the selected

write-buffer page, the operation aborts.

Note that if a Write Buffer address location is loaded

multiple times, the address/data pair counter is decre-

mented for every data load operation. The host system

must therefore account for loading a write-buffer loca-

tion more than once. The counter decrements for each

da ta lo ad op er atio n, n o t f o r e a ch un iqu e

write-buffer-address location. Also note, if an address

location is loaded more than once into the buffer, the

final data loaded for that address is programmed.

Once the specified number of write buffer locations

have been loaded, the system must then write the Pro-

gram Buffer to Flash command at the sector address.

Any other address and data combination aborts the

Write Buffer Programming operation. The device then

begins programming. Data polling should be used

while monitoring the last address location loaded into

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