AM29LV640MT110REF datasheet(14/66 Pages) AMD

14 / 66 page

Am29LV640MT/B

26190C8 February 1, 2007

D A TA

SH EE T

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

See See Reading Array Data on page 27 for more in-

formation. See the table, Read-Only Operations on

page 45 for timing specifications and to Figure 14 for

the timing diagram. Refer to the DC Characteristics

table for the active current specification on reading

array data.

Page Mode Read

The device is capable of fast page mode read and is

compatible with the page mode Mask ROM read oper-

ation. This mode provides faster read access speed

for random locations within a page. The page size of

the device is 4 words/8 bytes. The appropriate page is

selected by the higher address bits A(max)–A2. Ad-

dress bits A1–A0 in word mode (A1–A-1 in byte mode)

determine the specific word within a page. This is an

asynchronous operation; the microprocessor supplies

the specific word location.

The random or initial page access is equal to t

ACC or

CE and subsequent page read accesses (as long as

the locations specified by the microprocessor falls

within that page) is equivalent to t

PACC. When CE# is

deasserted and reasserted for a subsequent access,

the access time is t

ACC or tCE. Fast page mode ac-

cesses are obtained by keeping the “read-page ad-

dresses” constant and changing the “intra-read page”

addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V

IL, and OE# to VIH.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The

Word/Byte Program Command Sequence on page 29

has details on programming data to the device using

both standard and Unlock Bypass command se-

quences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 and Table 3 indicates

the address space that each sector occupies.

Refer to the DC Characteristics table for the active

current specification for the write mode. AC Character-

istics on page 45 contains timing specification tables

and timing diagrams for write operations.

Write Buffer

Write Buffer Programming allows the system to write a

maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming

time than the standard programming algorithms. See

Write Buffer on page 12 for more information.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the system asserts V

HH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

HH from the WP#/ACC pin returns the device to nor-

mal operation. Note that the WP#/ACC pin must not be

at V

HH for operations other than accelerated program-

ming, or device damage can result. In addition, no ex-

ternal pullup is necessary since the WP#/ACC pin has

internal pullup to V

CC.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. See Autoselect Mode on page 19 and Au-

toselect Command Sequence on page 28 for more in-

formation.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V

CC ± 0.3 V.

(Note that this is a more restricted voltage range than

IH.) If CE# and RESET# are held at VIH, but not within

CC ± 0.3 V, the device is in the standby mode, but the

standby current is greater. The device requires stan-

dard access time (t

CE) for read access when the de-

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