AM29SL400CB100REF datasheet(22/44 Pages) AMD

22 / 44 page

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A TA

SH EE T

If the output is low (Busy), the device is actively erasing or

programming. (This includes programming in the Erase Sus-

pend mode.) If the output is high (Ready), the device is

ready to read array data (including during the Erase Sus-

pend mode), or is in the standby mode.

Table 6 on page 22 shows the output s for RY/BY #.

Figure 14‚ on page 28, Figure 17‚ on page 31 , and

Figure 18‚ on page 32 shows RY/BY# for reset, program,

and erase operations, respectively.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid after the

rising edge of the final WE# pulse in the command sequence

(prior to the program or erase operation), and during the sec-

tor erase time-out.

During an Embedded Program or Erase algorithm operation,

successive read cycles to any address cause DQ6 to toggle

(The system may use either OE# or CE# to control the read

cycles). When the operation is complete, DQ6 stops tog-

gling.

After an erase command sequence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine which

sectors are erasing or erase-suspended. Alternatively, the

system can use DQ7 (see the subsection on DQ7: Data#

Polling‚ on page 19).

If a program address falls within a protected sector, DQ6 tog-

gles for approximately 1 µs after the program command se-

quence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is

complete.

Table 6 on page 22 shows the outputs for Toggle Bit I on

DQ6. Figure 6‚ on page 21 shows the toggle bit algorithm.

Figure 20‚ on page 33 shows the toggle bit timing diagrams.

Figure 21 shows the differences between DQ2 and DQ6 in

graphical form. See also the subsection on DQ2: Toggle Bit

II‚ on page 20.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates

whether a particular sector is actively erasing (that is, the

Embedded Erase algorithm is in progress), or whether that

sector is erase-suspended. Toggle Bit II is valid after the ris-

ing edge of the final WE# pulse in the command sequence.

The device toggles DQ2 with each OE# or CE# read cycle.

DQ2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. But DQ2

cannot distinguish whether the sector is actively erasing or is

erase-suspended. DQ6, by comparison, indicates whether

the device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for erasure.

Thus, both status bits are required for sector and mode infor-

mation. Refer to Table 6 on page 22 to compare outputs for

DQ2 and DQ6.

Figure 6‚ on page 21 shows the toggle bit algorithm in flow-

chart form, and the section DQ2: Toggle Bit II‚ on page 20

explains the algorithm. See also the DQ6: Toggle Bit I sub-

section. Figure 20‚ on page 33 shows the toggle bit timing di-

agram. Figure 21‚ on page 34 shows the differences

between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6‚ on page 21 for the following discussion.

Whenever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to deter-

mine whether a toggle bit is toggling. Typically, the system

would note and store the value of the toggle bit after the first

read. After the second read, the system would compare the

new value of the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or erase op-

eration. The system can read array data on DQ7–DQ0 on

the following read cycle.

However, if after the initial two read cycles, the system deter-

mines that the toggle bit is still toggling, the system also

should note whether the value of DQ5 is high (see the sec-

tion on DQ5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may

have stopped toggling just as DQ5 went high. If the toggle bit

is no longer toggling, the device has successfully completed

the program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and the

system must write the reset command to return to reading

array data.

The remaining scenario is that the system initially deter-

mines that the toggle bit is toggling and DQ5 has not gone

high. The system may continue to monitor the toggle bit and

DQ5 through successive read cycles, determining the status

as described in the previous paragraph. Alternatively, it may

choose to perform other system tasks. In this case, the sys-

tem must start at the beginning of the algorithm when it re-

turns to determine the status of the operation (top of

Figure 6‚ on page 21).

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