AM29SL400CB100REF datasheet(23/44 Pages) AMD

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January 23, 2007 Am29SL400C_00_A6

Am29SL400C

D A TA

SH EE T

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has ex-

ceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a 1. This is a failure condition that

indicates the program or erase cycle was not successfully

completed.

The DQ5 failure condition may appear if the system tries to

program a 1 to a location that is previously programmed to

“0.” Only an erase operation can change a 0 back to a 1.

Under this condition, the device halts the operation, and

when the operation has exceeded the timing limits, DQ5 pro-

duces a 1.

Under both these conditions, the system must issue the

reset command to return the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system

may read DQ3 to determine whether or not an erase opera-

tion has begun. (The sector erase timer does not apply to

the chip erase command.) If additional sectors are selected

for erasure, the entire time-out also applies after each addi-

tional sector erase command. When the time-out is com-

plete, DQ3 switches from 0 to 1. If the time between

additional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not monitor

DQ3. See also Sector Erase Command Sequence‚ on

page 16.

After the sector erase command sequence is written, the

system should read the status on DQ7 (Data# Polling) or

DQ6 (Toggle Bit I) to ensure the device has accepted the

command sequence, and then read DQ3. If DQ3 is 1, the in-

ternally controlled erase cycle has begun; all further com-

mands (other than Erase Suspend) are ignored until the

erase operation is complete. If DQ3 is 1, the device will ac-

cept additional sector erase commands. To ensure the com-

mand has been accepted, the system software should check

the status of DQ3 prior to and following each subsequent

sector erase command. If DQ3 is high on the second status

check, the last command might not have been accepted.

Table 6 on page 22 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

Read toggle bit twice to determine whether or not it is toggling.

See text.

Recheck toggle bit because it may stop toggling as DQ5

changes to 1. See text.

Figure 6.

Toggle Bit Algorithm

(Notes

1, 2)

(Note 1)

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