AS7341 datasheet(36/69 Pages) OSRAM

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AS7341

Datasheet

• PUBLIC

DS000504

• v3-00 • 2020-Jun-25

│ 35

EDGE Register (Address 0x72)

Figure 46:

EDGE Register

Addr: 0x72

EDGE

Bit

Bit Name

Default

Access

Bit Description

7:0

SYNC_EDGE

Number of falling SYNC-edges between start and

stop of integration in mode SYND

Number of edges = SYNC_EDGE + 1

FD_TIME Register (Address 0xD8, 0xDA)

The register FD Time 1 and FD Time 2 can be used to configure the integration time and gain (ADC 5)

of the flicker detection independently from the other ADCs. The FD_TIME register is an 11-bit register

with the MSB in register 0xDA (bit 10:8) and the LSB in register 0xD8 (bit 7:0). The bit FDEN (register

0x80) must be set to “1” in order to use the FD_TIME registers. If the bit FDEN is not set, ADC5 runs

automatically with the same gain and integration time as ADC0 to ADC4.

Equation 4: Calculating the flicker detection integration time

��_�� = ��_�� × 2.78µ��

Figure 47:

FD Time Register

Addr: 0xD8

FD_TIME_1

Bit

Bit Name

Default

Access

Bit Description

7:0

FD_TIME [7:0]

LSB of flicker detection integration time

Note: must not be changed during FDEN = 1 and

PON = 1.

AS7341 数据表(PDF) 36 Page - OSRAM GmbH

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