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AS7341 数据表(PDF) 44 Page - OSRAM GmbH |
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AS7341 数据表(HTML) 44 Page - OSRAM GmbH |
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44 / 69 page ![]() Document Feedback AS7341 Register Description Datasheet • PUBLIC DS000504 • v3-00 • 2020-Jun-25 68 │ 43 Addr: 0x87 SP _TH_H_MSB Bit Bit Name Default Access Bit Description Both SP_TH_H registers are combined to a 16-bit threshold. If the value captured by channel 0 is above the high threshold and the APERS value is reached the bit SP_IEN is set and an interrupt is generated. CFG12 Register (Address 0xB5) Figure 61: CFG12 Register Addr: 0xB5 CFG12 Bit Bit Name Default Access Bit Description 7:3 reserved 0 reserved 2:0 SP_TH_CH 0 RW Spectral Threshold Channel. Sets the channel used for interrupts, persistence and the AGC, if enabled, to determine device status and gain settings. VALUE CHANNEL 0 CH0 1 CH1 2 CH2 3 CH3 4 CH4 |
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