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TSL2521 数据表(PDF) 63 Page - OSRAM GmbH |
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TSL2521 数据表(HTML) 63 Page - OSRAM GmbH |
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63 / 81 page ![]() Page 62 Datasheet, Public Document Feedback [v3-00] 2022-Dec-21 TSL2521 − Register O ver view VSYNC_GPIO_INT Register Figure 79: VSYNC_GPIO_INT Note(s): 1. Return to the Register Map (0xF8). Addr: 0xF8 VSYNC_GPIO_INT Bit Field Reset Type Bit Description 7Reserved 0 6INT_INVERT 0 R/W If set to “1” the INT pin output is inverted. This applies to all output signals as selected in INT_PINMAP 5INT_IN_EN 0 R/W If programmed to “1” the INT pin is set as input. Please observe that the connected net must not be floating since INT is an open drain input. 4 INT_IN 0 R External HIGH or LOW value applied to INT pin 3VSYNC_GPIO_INVERT 0 R/W If set to “1” the VSYNC/GPIO pin output is inverted. This applies to all output signals as selected in VSYNC_GPIO_ PINMAP 2 VSYNC_GPIO_IN_EN 0 R/W If programmed to “1” the VSYNC/GPIO pin is set as input. Please observe that the connected net must not be floating since VSYNC/GPIO is an open drain input 1 VSYNC_GPIO_OUT 1 R/W Programs the VSYNC/GPIO pin HI or LOW. Since the pin is an open drain I/O pin, the default value is HIGH to avoid any unintended power consumption through pull-up resistor. The routed internal signal is selected in VSYNC_GPIO_PINMAP. 0 VSYNC_GPIO_IN 0 R External HIGH or LOW value applied to VSYNC/GPIO pin. |
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