TSL2521 datasheet(38/81 Pages) OSRAM

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Datasheet, Public

Page 37

[v3-00] 2022-Dec-21

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TSL2521 − Register Overview

CFG4 Register

Figure 44:

CFG4

Note(s):

1. Return to the Register Map (0xA5).

Addr: 0xA5

CFG4

Bit

Field

Reset

Type

Bit Description

7Reserved

MOD_CALIBRATION_

NTH_ITERATION_

STEP_ENABLE

0R/W

Enable a modulator calibration with nth iterations

per sequencer step instead of waiting for a full round

for all sequencers to be finished. In case of AGC

enabled (MOD_CALIB_NTH_ITERATION_AGC_

ENABLE) this bit must be set “0”, otherwise AGC will

not properly work.

MEASUREMENT_

SEQUENCER_AGC_

PREDICT_TARGET_

LEVEL

0R/W

Sets the target measurement levels for AGC

prediction.

0: 50% of max value

1: 25% of max value

MEASURMENT_

SEQUENCER_

SINT_PER_STEP

0R/W

Invokes the system interrupt SINT_MEASUREMENT_

SEQUENCER per sequencer step instead of after a full

sequencer round.

OSC_TUNE_NO_

RESET

0R/W

OSC_TUNE is set to "0" at each transition of PON

from "0" to "1". If OSC_TUNE_NO_RESET is asserted,

OSC_TUNE is not reset to "0".

2Reserved

1:0

MOD_ALS_FIFO_

DATA_FORMAT

0R/W

Sets the format for ALS data written to FIFO. Please

observe readout pattern if digital or analog

saturation has occurred

00: 16-bit (0xFFFF is encoded as analog saturation,

0xFFFE is encoded as digital saturation).

01: 24-bit (0xFFFFFF is encoded as analog saturation,

0xFFFFFE is encoded as digital saturation).

10: Reserved.

11: 32-bit (0xFFFFFFFF is encoded as analog,

saturation, no digital saturation will happen).

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