TSL25413 datasheet(10/39 Pages) OSRAM

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Datasheet, Public

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[v2-00] 2023-Mar-10

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TSL2541 − Detailed Description

the final byte the master places an ACK on the bus (9TH clock

pulse). Termination of the Read transaction is indicated by a

NACK being placed on the bus by the master, followed by STOP.

The I²C bus protocol was developed by Philips (now NXP). For

a complete description of the I²C protocol, please review the

NXP I²C design specification at:

www.i2c-bus.org/references/

Timing Diagrams

Figure 11:

I²C Timing

Principles of Operation

System State Machine

An internal state machine provides system control of the ALS,

proximity detection, and power management features of the

device. At power up, an internal power-on-reset initializes the

device and puts it in a low power Sleep state. When a write on

I²C bus to the Enable register (0x80) PON bit is set, the device

transitions to the Idle state. If PON is disabled, the device will

return to the Sleep state to save power. Otherwise, the device

will remain in the Idle state until the ALS function is enabled.

Once enabled, the device will execute the ALS and Wait states

in sequence as indicated in Figure 12. Upon completion, the

device will automatically begin a new ALS-Wait cycle as long as

PON and AEN remain enabled. If the ALS function generates an

interrupt and the Sleep-After-Interrupt (SAI) feature is enabled,

the device will transition to the Sleep state and remain in a

low-power mode until an I²C command is received clearing the

interrupts in the STATUS register. See Interrupts for additional

information.

TSL25413 数据表(PDF) 10 Page - OSRAM GmbH