TSL25413 datasheet(14/39 Pages) OSRAM

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Datasheet, Public

Page 13

[v2-00] 2023-Mar-10

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TSL2541 − Register Description

ATIME Register (Address 0x81)

Figure 15:

ATIME Register

The ATIME register controls the integration time of the ALS

ADCs. The timer is implemented with a down counter with 0x00

as the terminal count. The timer is clocked at a 2.8ms nominal

rate. Loading 0x00 will generate a 2.8ms integration time,

loading 0x01 will generate a 5.6ms integration time, and so

forth. The RC oscillator runs at 8MHz nominal rate. This gets

divided by 11 to generate the integration clock of 727kHz. One

count in ATIME (nominal 2.8ms) are 2.81ms. This is 2048

integration clock cycles: 125ns*11*8*256=2.81ms.

Addr: 0x81

ATIME

Bit

Bit Name

Default

Access

Bit Description

7:0

ATIME

0x00

ALS value that specifies the integration time in 2.81ms

intervals. 0x00 indicates 2.8ms. The maximum ALS value

depends on the integration time. For every 2.81ms, the

maximum value increases by 1024. This means that to

be able to reach ALS full scale, the integration time has

to be at least 64*2.8ms.

Value

Integration

Cycles

Integration

Time

Maximum

ALS Value

0x00

2.8ms

1023

0x01

5.6ms

2047

……

…

0x3F

180ms

65535

……

…

0xFF

256

721ms

65535

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