TSL25413 datasheet(15/39 Pages) OSRAM

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[v2-00] 2023-Mar-10

TSL2541 − Register Description

WTIME Register (Address 0x83)

Figure 16:

WTIME Register

The wait timer is implemented using a down counter.

Wait time = (value +1) x 2.8ms. If WLONG is enabled then

Wait time = (value +1) x 2.8ms x 12.

AILTL Register (Address 0x84)

Figure 17:

AILTL Register

The Visible (Vis) channel is compared against low-going 16-bit

threshold value set by AILTL and AILTH.

Addr: 0x83

WTIME

Bit

Bit Name

Default

Access

Bit Description

7:0

WTIME

0x00

Value that specifies the wait time between ALS cycles in

2.81ms increments.

Value

Increments

Wait Time

0x00

2.8ms (33.8ms)

0x01

5.6ms (67.6ms)

………

0x3F

180ms (2.16s)

………

0xFF

256

721ms (8.65s)

Addr: 0x84

AILTL

Bit

Bit Name

Default

Access

Bit Description

7:0

AILTL

0x00

This register sets the low byte of the LOW ALS threshold.

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