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ams Datasheet

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[v1-00] 2016-Apr-05

TSL2580, TSL2581 − Register Set

Timing Register (01h)

The TIMING register controls the internal integration time of the

ADC channels in 2.7 ms increments. The TIMING register

defaults to 00h at power on.

Figure 29:

Timing Register

Note(s):

1. The Send Byte protocol cannot be used when ITIME is greater than 127 (for example ITIME[7] = 1) since the upper bit is set aside for

write transactions in the COMMAND register.

76

5

4

3

2

1

0

ITIME

Field

Bits

Description

ITIME

7:0

Integration Cycles. Specifies the integration time in 2.7-ms intervals. Time is expressed

as a 2’s complement number. So, to quickly work out the correct value to write: (1)

determine the number of 2.7-ms intervals required, and (2) then take the 2’s

complement. For example, for a 1 × 2.7-ms interval, 0xFF should be written. For 2 ×

2.7-ms intervals, 0xFE should be written. The maximum integration time is 688.5 ms

(00000001b).

Writing a 0x00 to this register is a special case and indicates manual timing mode. See

CONTROL and MANUAL INTEGRATION TIMER Registers for other device options related

to manual integration.

INTEG_CYCLES

TIME

VALUE

−

Manual integration

00000000

1

2.7 ms

11111111

2

5.4 ms

11111110

19

51.3 ms

11101101

37

99.9 ms

11011011

74

199.8 ms

10110110

148

399.6 ms

01101100

255

688.5 ms

00000001