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数据搜索系统，热门电子元器件搜索 |
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MPC862 数据表(PDF) 6 Page - Freescale Semiconductor, Inc |
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MPC862 数据表(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 88 page  MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 6 Freescale Semiconductor Features — Sleep—All units disabled except RTC, PIT, time base, and decrementer with PLL active for fast wake up — Deep sleep—All units disabled including PLL except RTC, PIT, time base, and decrementer. — Power down mode— All units powered down except PLL, RTC, PIT, time base and decrementer • Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — Supports conditions: = ≠ < > — Each watchpoint can generate a break point internally • 3.3 V operation with 5-V TTL compatibility except EXTAL and EXTCLK • 357-pin plastic ball grid array (PBGA) package • Operation up to 100MHz The MPC862/857T/857DSL is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the system integration unit (SIU), and the communication processor module (CPM). The MPC862P/862T block diagram is shown in Figure 1. The MPC857T/857DSL block diagram is shown in Figure 2. |
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