ST25R200 datasheet(86/88 Pages) STMICROELECTRONICS

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Table 54.

Over/Undershoot protection configuration register ............................................ 53

Table 55.

Overshoot pattern register............................................................. 53

Table 56.

Undershoot pattern register............................................................ 54

Table 57.

Wake-up configuration register 1 ........................................................ 54

Table 58.

Typical wake-up period/time ........................................................... 54

Table 59.

Wake-up configuration register 2 ........................................................ 55

Table 60.

Measurement pulse length ............................................................ 55

Table 61.

I-Channel WU configuration register ...................................................... 56

Table 62.

I-Channel WU difference register ........................................................ 56

Table 63.

I-Channel WU display ADC register ...................................................... 57

Table 64.

I-Channel WU reference register ........................................................ 57

Table 65.

I-Channel WU display calibration register .................................................. 57

Table 66.

Q-Channel WU configuration register ..................................................... 58

Table 67.

Channel WU difference register ......................................................... 58

Table 68.

Q-Channel WU display ADC register ..................................................... 59

Table 69.

Q-Channel WU reference register ....................................................... 59

Table 70.

Q-Channel WU display calibration register ................................................. 59

Table 71.

TX frame register 1 ................................................................. 60

Table 72.

Tx frame register 2 .................................................................. 60

Table 73.

FIFO status register 1................................................................ 61

Table 74.

FIFO status register 2................................................................ 61

Table 75.

Collision display register .............................................................. 62

Table 76.

IRQ mask register 1 ................................................................. 62

Table 77.

IRQ mask register 2 ................................................................. 63

Table 78.

IRQ mask register 3 ................................................................. 63

Table 79.

IRQ status register 1 ................................................................ 64

Table 80.

IRQ status register 2 ................................................................ 64

Table 81.

IRQ status register 3 ................................................................ 65

Table 82.

IC identity register .................................................................. 65

Table 83.

Direct commands................................................................... 66

Table 84.

Observation access 1 ................................................................ 69

Table 85.

TAD1/TAD2 test mode ............................................................... 69

Table 86.

Observation register 2 ............................................................... 69

Table 87.

TAD1/TAD2 test signal (tm_rxwu_tad=3) ................................................... 70

Table 88.

TAD1/TAD2 test signal (tm_rxwu_tad=6) ................................................... 70

Table 89.

Absolute maximum ratings ............................................................ 71

Table 90.

Operating conditions ................................................................ 71

Table 91.

Characteristics of CMOS I/Os .......................................................... 72

Table 92.

Electrical characteristics (VDD = 2.7 V, VDD_IO = 2.7 V) ......................................... 73

Table 93.

Electrical characteristics (VDD = 3.3 V, VDD_IO = 3.3 V) ......................................... 74

Table 94.

Electrical characteristics (VDD = 5.5 V, VDD_IO = 5.5 V) ......................................... 75

Table 95.

SPI interface characteristics(up to 10 MHz) ................................................. 76

Table 96.

UFQFPN24 - Mechanical data .......................................................... 78

Table 97.

Ordering information scheme........................................................... 79

Table 98.

Document revision history ............................................................. 80

ST25R200

List of tables

DS13658 - Rev 2

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