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PIC18F258-E/PSQTP 数据表(PDF) 36 Page - Microchip Technology |
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PIC18F258-E/PSQTP 数据表(HTML) 36 Page - Microchip Technology |
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36 / 402 page  PIC18FXX8 DS41159E-page 34 © 2006 Microchip Technology Inc. RXB0DLC PIC18F2X8 PIC18F4X8 -xxx xxxx -uuu uuuu -uuu uuuu RXB0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL PIC18F2X8 PIC18F4X8 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON PIC18F2X8 PIC18F4X8 000- 0000 000- 0000 uuu- uuuu RXB1D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC PIC18F2X8 PIC18F4X8 -xxx xxxx -uuu uuuu -uuu uuuu RXB1EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL PIC18F2X8 PIC18F4X8 xxxx x-xx uuuu u-uu uuuu u-uu RXB1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON PIC18F2X8 PIC18F4X8 000- 0000 000- 0000 uuu- uuuu TXB0D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0DLC PIC18F2X8 PIC18F4X8 -x-- xxxx -u-- uuuu -u-- uuuu TXB0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). |
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