PIC18F258-ESLASHPSQTP datasheet(46/402 Pages) MICROCHIP

46 / 402 page

PIC18FXX8

DS41159E-page 44

4.9

Data Memory Organization

The data memory is implemented as static RAM. Each

allowing up to 4096 bytes of data memory. Figure 4-6

shows

the

data

memory

organization

for

the

PIC18FXX8 devices.

The data memory map is divided into as many as

16 banks that contain 256 bytes each. The lower 4 bits

of the Bank Select Register (BSR<3:0>) select which

bank will be accessed. The upper 4 bits for the BSR are

not implemented.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratchpad operations in the user’s appli-

cation. The SFRs start at the last location of Bank 15

(FFFh) and grow downwards. GPRs start at the first

location of Bank 0 and grow upwards. Any read of an

unimplemented location will read as ‘0’s.

The entire data memory may be accessed directly or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of

the File Select Register (FSR). Each FSR holds a

12-bit address value that can be used to access any

location in the data memory map without banking.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing or by the use of the MOVFF instruction. The

MOVFF

instruction is a two-word/two-cycle instruction,

that moves a value from one register to another.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle,

regardless of the current BSR values, an Access Bank

is implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 4.10

“Access Bank” provides a detailed description of the

Access RAM.

4.9.1

GENERAL PURPOSE

The register file can be accessed either directly or

indirectly. Indirect addressing operates through the File

Select Registers (FSR). The operation of indirect

addressing

shown

Section 4.12

“Indirect

Addressing, INDF and FSR Registers”.

Enhanced MCU devices may have banked memory in

the GPR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other Resets.

Data RAM is available for use as GPR registers by all

instructions. Bank 15 (F00h to FFFh) contains SFRs.

All other banks of data memory contain GPR registers,

starting with Bank 0.

4.9.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

given in Table 4-1.

The SFRs can be classified into two sets: those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described in this section, while those related

to the operation of the peripheral features are

described in the section of that peripheral feature.

The

SFRs

are

typically

distributed

among

the

peripherals whose functions they control.

The unused SFR locations will be unimplemented and

read as ‘0’s. See Table 4-1 for addresses for the SFRs.

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