PIC18F258-ESLASHPSQTP datasheet(81/402 Pages) MICROCHIP

81 / 402 page

DS41159E-page 79

PIC18FXX8

8.1

INTCON Registers

The INTCON registers are readable and writable regis-

ters which contain various enable, priority and flag bits.

Because of the number of interrupts to be controlled,

PIC18FXX8 devices have three INTCON registers.

They are detailed in Register 8-1 through Register 8-3.

INTCON: INTERRUPT CONTROL REGISTER

Note:

Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

interrupt enable bit. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

This feature allows software polling.

R/W-0

R/W-x

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

bit 7

bit 0

bit 7

GIE/GIEH: Global Interrupt Enable bit

When IPEN (RCON<7>) = 0:

= Enables all unmasked interrupts

= Disables all interrupts

When IPEN (RCON<7>) = 1:

= Enables all high priority interrupts

= Disables all priority interrupts

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN (RCON<7>) = 0:

= Enables all unmasked peripheral interrupts

= Disables all peripheral interrupts

When IPEN (RCON<7>) = 1:

= Enables all low priority peripheral interrupts

= Disables all low priority peripheral interrupts

bit 5

TMR0IE: TMR0 Overflow Interrupt Enable bit

= Enables the TMR0 overflow interrupt

= Disables the TMR0 overflow interrupt

bit 4

INT0IE: INT0 External Interrupt Enable bit

= Enables the INT0 external interrupt

= Disables the INT0 external interrupt

bit 3

RBIE: RB Port Change Interrupt Enable bit

= Enables the RB port change interrupt

= Disables the RB port change interrupt

bit 2

TMR0IF: TMR0 Overflow Interrupt Flag bit

= TMR0 register has overflowed (must be cleared in software)

= TMR0 register did not overflow

bit 1

INT0IF: INT0 External Interrupt Flag bit

= The INT0 external interrupt occurred (must be cleared in software by reading PORTB)

= The INT0 external interrupt did not occur

bit 0

RBIF: RB Port Change Interrupt Flag bit

= At least one of the RB7:RB4 pins changed state (must be cleared in software)

= None of the RB7:RB4 pins have changed state

Note:

A mismatch condition will continue to set this bit. Reading PORTB will end the

mismatch condition and allow the bit to be cleared.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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