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STW5094AD 数据表(PDF) 29 Page - STMicroelectronics |
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STW5094AD 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 51 page  29/51 STw5094A Figure 10. Audio interface (AU I/F) formats in I2S master and slave modes LRCK SCK SDI 16 1 2 13 14 15 16 1 2 13 14 15 16 Left channel Right channel MSB LSB MSB LSB I2S Format (delayed), Data word 16 bit, MSB first (default) LRCK SCK SDI X 1 2 17 18 x 1 2 Left channel Right channel I2S Format (delayed), Data word 18 bit, Left justified, LSB first x LSB MSB LSB 16 SCK 17 18 x x MSB 32 SCK LRCK SCK SDI 1 2 3 23 24 x 2 3 Left channel Right channel Non-delayed Format, Data word 24 bit, Left justified, MSB first, LRCK polarity inverted 1 MSB LSB MSB 23 24 x 1 LSB 32 SCK LRCK SCK SDI 1 2 3 14 15 16 1 2 3 14 15 16 1 Left channel Right channel Non-delayed Format, SCK polarity inverted, Data word 16 bit, LSB first 16 SCK MSB MSB LSB LSB For the other possible formats see Control Register CR16 description LRCK SCK SDI x 18 Left channel Right channel Data word 18 bit, Right justified, MSB first x MSB x 1 2 x LSB 32 SCK 18 x x MSB x 1 2 LSB 32 SCK 32 SCK 32 SCK 16 SCK 16 SCK |
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