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STw5094A

Figure 13. Audio interface (AU I/F) formats in SPI mode

LRCK

SCK

SDI

1

2

15

16

1

Left or Right channel

Right or Left channel

MSB

LSB

SCK polarity normal, Data word 16 bit

SCK polarity inverted, Data word 18 bit

2

32 SCK

NOTE: In SPI-mode the first high to low transition on LRCK after power-up defines the Left channel of the first couple of audio data

MSB

XX

X

For the other possible formats see Control Register CR16 description

LRCK

SCK

SDI

1

2

17

18

MSB

LSB

XX

X

1

2

MSB

X

and of all the subsequent couples of Left/Right audio data.

Left or Right channel

Right or Left channel

WRITE

SINGLE BYTE

START

DEVICE ADDRESS

REG n ADDRESS

REG n DATA IN

ACK

ACK

ACK

STOP

WRITE

MULTI BYTE

START

DEVICE ADDRESS

REG n ADDRESS

REG n DATA IN

ACK

ACK

ACK

STOP

REG n+m DATA IN

ACK

m+1 data bytes

CURRENT ADDR

START

DEVICE ADDRESS

Current REG DATA OUT

ACK

NO ACK

STOP

READ

SINGLE BYTE

CURRENT ADDR

START

DEVICE ADDRESS

Current REG DATA OUT

ACK

NO ACK

STOP

READ

MULTI BYTE

Curr REG+m DATA OUT

ACK

ACK

ACK

m+1 data bytes

START

DEVICE ADDRESS

REG n ADDRESS

ACK

ACK

START

DEVICE ADDRESS

REG n DATA OUT

ACK

NO ACK

STOP

RANDOM ADDR

READ

SINGLE BYTE

RANDOM ADDR

READ

MULTI BYTE

START

DEVICE ADDRESS

REG n ADDRESS

ACK

ACK

START

DEVICE ADDRESS

NO ACK

STOP

REG n+m DATA OUT

ACK

ACK

m+1 data bytes

REG n DATA OUT

ACK

11100011

11100011

11100010

11100010

11100010

11100010

11100011

11100011