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CS4341 数据表(PDF) 13 Page - Cirrus Logic

部件名 CS4341
功能描述  24-Bit, 96 kHz Stereo DAC with Volume Control
PDF  34 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS4341 数据表(HTML) 13 Page - Cirrus Logic

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CS4341
DS298F5
13
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™)
Notes: 10. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For fsclk < 1 MHz.
Parameter
Symbol
Min
Max
Unit
SPI Mode
CCLK Clock Frequency
fsclk
-6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling
(Note 10)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
-ns
CCLK High Time
tsch
-ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 11)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 12)
tr2
-100
ns
Fall Time of CCLK and CDIN
(Note 12)
tf2
-100
ns
1
MCLK
-----------------
1
MCLK
-----------------
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t csh
t spi
t srs
RST
Figure 15. Control Port Timing - SPI Mode



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