CS4341

DS298F5

25

6. REGISTER DESCRIPTION

NOTE: All registers are read/write in I²C Mode and write only in SPI mode, unless otherwise stated.

6.1

MCLK CONTROL (ADDRESS 00H)

Default = 0

0 - Disabled

1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.

6.2

MODE CONTROL (ADDRESS 01H)

Default = 1

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio

samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting

is done independently for each channel. The quiescent voltage on the output will be retained and the

Mute Control pin will go active during the mute period. The muting function is affected, similar to vol-

ume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address

02h) register.

7

654

32

10

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

MCLKDIV

Reserved

0

000

00

00

7

654

32

10

AMUTE

DIF2

DIF1

DIF0

DEM1

DEM0

POR

PDN

1

000

00

11