CS4341

26

DS298F5

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the

Digital Interface Format and the options are detailed in Figures 17 through 19.

Default = 00

00 - Disabled

01 - 44.1 kHz

10 - 48 kHz

11 - 32 kHz

Function:

Implementation of the standard 15

µs/50µs digital de-emphasis filter response, Figure 20, requires re-

configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample

rates.

NOTE: De-emphasis is only available in Single-Speed Mode.

Default = 1

0 - Disabled

1 - Enabled

Function:

the quiescent voltage during power-on or power-down. Please refer to section 4.6 for implementation

details.

Default = 1

0 - Disabled

1 - Enabled

Function:

The device will enter a low-power state when this function is enabled. The power-down bit defaults to

‘enabled’ on power-up and must be disabled before normal operation can occur. The contents of the

control registers are retained in this mode.

DIF2

DIF1

DIF0

DESCRIPTION

Format

FIGURE

0

0

0

I²S, up to 24-bit data, 64Fs Internal SCLK

0

17

0

0

1

I²S, up to 16-bit data, 32Fs Internal SCLK

1

17

0

1

0

Left Justified, up to 24-bit data,

2

18

0

1

1

Right Justified, 24-bit data

3

19

1

0

0

Right Justified, 20-bit data

4

19

1

0

1

Right Justified, 16-bit data

5

19

1

1

0

Right Justified, 18-bit data

6

19

1

1

1

Identical to Format 1

1

17

Table 5. Digital Interface Format