TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

36

POST OFFICE BOX 655303

receiver squelch parameters

10BASE-T

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Vthp

Positive-squelch receiver threshold voltage

250

mV

Vthn

Negative-squelch receiver threshold voltage

–250

mV

Vthd

Data receiver threshold voltage

75

mV

100BASE-TX

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Vth

Receiver differential voltage to maintain link

200

mV

PARAMETER MEASUREMENT INFORMATION

Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V.

Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the

level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low is 0.8 V.

For a low-to-high transition, the level at which the signal is no longer said to be low is 0.8 V and the level at which

the signal is said to be high is 2 V, as shown in the following diagram.

2 V (high)

0.8 V (low)

The rise and fall times are not specified, but are assumed to be those of standard TTL devices, which are typically

1.5 ns.

test measurement

The test and load circuit shown in Figure 27 represents the programmable load of the tester-terminal electronics

used to verify timing parameters of the TNETE2101 output signals.

TTL OUTPUT TEST LOAD

CL

IOH

VLOAD

IOL

Test

Point

TTL

Output

Under

Test

Where: IOL

= Refer to IOL in recommended operating conditions.

IOH

= Refer to IOH in recommended operating conditions.

VLOAD = 1.5 V, typical dc-level verification or

1.5 V, typical timing verification

CL

= 45 pF, typical load-circuit capacitance

Figure 27. Test and Load Circuit