TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

5

POST OFFICE BOX 655303

Terminal Functions (Continued)

LED status

TERMINAL

TYPE

I/O

DESCRIPTION

NAME

NO.

TYPE

I/O

DESCRIPTION

LACTIVITY

24

LED

O

Activity indicator. LACTIVITY lights an attached LED in response to receive and transmit activity

within the PHY.

LDUPCOL

25

LED

O

Duplex/collision indicator. LDUPCOL lights an attached LED in response to a network collision when

the PHY is in half-duplex mode of operation. The LED is illuminated continuously when the PHY is

in full-duplex mode.

LLINK

27

LED

O

Link status indicator. LLINK lights an attached LED when the PHY has established a valid link with

its partner. If autonegotiation is enabled, the driver flashes the LED during negotiation to indicate that

it is attempting to establish a link. This is useful because a negotiation takes a minimum of 3 seconds

(considerably longer if next-page information also is being exchanged), and the user may be tempted

to remove the cable if the link light does not illuminate immediately. The user also is alerted to a

network misconfiguration (where no common ability exists between the two link partners) by a

continuously flashing LED.

LSPEED

28

LED

O

Link speed indicator. LSPEED lights an attached LED when the PHY has established a valid

100BASE-TX link with its partner.

MII interface

TERMINAL

TYPE†

I/O

DESCRIPTION

NAME

NO.

TYPE†

I/O

DESCRIPTION

MCOL

(CDEVSEL4)

56

5-V TTL

I/O

Collision detect. MCOL indicates that the PHY is receiving data while simultaneously

transmitting. MCOL does not assert in full-duplex mode. The value of MCOL is latched on the

rising edge of MRST for use as CDEVSEL4, bit 4, of the MII device-select address.

MDCLK

43

5-V TTL

I

Management

data

clock.

MDCLK

clocks

serial

management

interface

to

the

physical-media-dependent (PMD) chip.

MDIO

42

5-V TTL

I/O

Management data I/O. MDIO is serial management interface to the PMD chip. MDIO is

synchronous to MDCLK.

MRCLK

54

5-V TTL

O

Receive clock. Receive clock source from the PHY. MRCLK is 2.5 MHz in 10BASE-T mode and

25 MHz in 100BASE-TX mode.

MCRS

55

5-V TTL

O

Carrier sense. MCRS asserts when the PHY initiates a frame reception.

MRST

41

5-V TTL

I

MII reset. MRST is the reset signal to the PMD front end (active low).

MRXD3

MRXD2

MRXD1

MRXD0

47

48

50

52

5-V TTL

O

Receive data. MRXD3–MRXD0 are nibble receive data bits 3–0 from the PHY. Data is

synchronous to MRCLK.

MRXDV

46

5-V TTL

O

Receive data valid. MRXDV indicates that data on MRXD0–MRXD3 is valid. MRXDV is

synchronous to MRCLK.

MRXER

45

5-V TTL

O

Receive error. MRXER indicates reception of a coding error on received data. MRXER is

synchronous to MRCLK.

MTCLK

66

5-V TTL

O

Transmit clock. MTCLK is the transmit clock source from the PHY. This clock is 2.5 MHz in

10BASE-T mode and 25 MHz in 100BASE-TX mode.

MTXD3

MTXD2

MTXD1

MTXD0

60

61

62

63

5-V TTL

I

Transmit data. MTXD3–MTXD0 are nibble transmit data bits 3–0 from the MAC. Data is

synchronous to MTCLK.

† 5-V TTL terminals are 5-V tolerant if VDD5 is connected to 5 V.