TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

9

POST OFFICE BOX 655303

functional description

10BASE-T/100BASE-TX differential line transmitter function

The TNETE2101 differential line drivers are designed to drive at least 100 m of CAT5 cable in 100BASE-TX

mode and in excess of 100 m of CAT3 (or CAT5) cable in 10BASE-T mode. Three transmitter-output terminals

(including a center-tap connection) interface to a single transformer for both operating modes. This simplifies

the external connection to a single RJ-45 socket connected directly to the transformer secondary winding (see

Figure 2).

The TNETE2101 incorporates on-chip wave shaping for 10BASE-T transmission and rise-time control for

100BASE-TX transmission, which enables the device to interface directly to the magnetics without using

external components, other than two termination resistors. The functional block diagram illustrates the

TNETE2101 transmitter function for a single 10BASE-T/100BASE-TX PHY channel.

10BASE-T/100BASE-TX differential line receiver function

The two receiver-input terminals of the TNETE2101 must be connected to the physical-media interface (PMI)

through an external isolation transformer. The receiver circuitry establishes its own common-mode input bias

voltage, therefore, no external resistor divider-biasing network is required. A simple termination network

consisting of two resistors and one capacitor is recommended (see Figure 2). Data received from the network

is output on the MRXD data nibble of the MII and synchronized to the rising edge of the corresponding MRCLK

signal. The MRCLK frequency automatically adjusts to 2.5 MHz in 10BASE-T mode or 25 MHz in 100BASE-TX

mode.

A single receiver-input pair supports both speed modes, with all multiplexing functions performed internally to

the device.

The 10BASE-T receiver smart-squelch function allows incoming data to pass only if the input amplitude is

greater than a minimum signal threshold and a specific pulse sequence is received. This prevents input data

being affected by impulse line noise that is mistaken for signal or link activity. The squelch circuits quickly

deactivate if received pulses exceed the specifications; therefore, long pulses are not mistaken as link pulses.

The 100BASE-TX receiver decodes the MLT-3 waveform and provides a data nibble on MRXD0–MRXD3. After

MLT-3 signal is received, the signal is immediately amplified and equalized. This allows reception over a

minimum of 100 m of CAT5 cable. The low-frequency component of the MLT-3 signal, often referred to as BLW,

is removed. BLW can be a consequence of long periods without data transitions in transformer-coupled circuits.

The ideal MLT-3 then is internally converted to non-return-to-zero information (NRZI), then resynchronized to

its own recovered clock using a digital phase-locked-loop (PLL) technique. The reclocked data then is

deserialized into 5-bit code groups, descrambled, and 5B4B decoded. When a start-of-stream delimiter is

detected in the 5B data stream, the next frame is output on the MII. The functional block diagram illustrates the

TNETE2101 receiver function for a single 10BASE-T/100BASE-TX PHY channel.